Force inout port

SystemVerilog
2

In reply to robert.liu:

I am not sure what description you are looking for if you already know the example works the way you think it should. The LRM cannot provide the interaction of every possible feature used with another feature. The bind construct is essentially the same as writing

module test;
 wire foobar;
 probe probe_i(.foobar(foobar));
endmodule
 
module probe(inout foobar);
 initial force foobar = 1'bx;
endmodule