For loop to assign multiple variables

SystemVerilog
,
5

In reply to dave_59:

Hi Dave,

I will try that but can we write the assign statements using defines?
Ex:

`define M_SUB(i) ``i
for( genvar i = 0; i < 100; i++ )
begin : iter_i
  assign var_inst`M_SUB(i)	=   dut.module1.module2.reg_cfg[i].var;
end

Thanks.