For loop and a random variable

SystemVerilog
,
4

In reply to syed taahir ahmed:

You still didn’t show the declarations of all variables in the code. But I think replacing

entry_add_index = $urandom_range(0,($size(test_entries_add)-1));

with

void'(randomize (entry_add_index) with {
    entry_add_index <$size(test_entries_add);
    unique {entry_add_index,test_entries_added};
});

should work.