In reply to ben@SystemVerilog.us:
IF we and p1 and p2 if ACK is not present throughout the timeout p2(ap_ABS2BBS) will fail and assertion will be error even if the p2 is fine.
Can you show example how to OR two properties .
In reply to ben@SystemVerilog.us:
IF we and p1 and p2 if ACK is not present throughout the timeout p2(ap_ABS2BBS) will fail and assertion will be error even if the p2 is fine.
Can you show example how to OR two properties .