In reply to ben@SystemVerilog.us:
// Conditions for state to go into BBS without the ack
ap_ABS_till_BBS: assert property(@ (posedge clk)
$rose(state==ABS) |-> ##1 state==ABS[*1:99] ##0 state==BBS);
fails if ack is present .
FSM should move to next state if ACK is not present in this case , But only after 100 clk cycles. This assertion allows it to check before timeout