In reply to Abuzar Gaffari:
It would help to have more details about your problem. As previously mentioned, SystemVerilog provides no way to reference identifiers via strings. Compiled languages like C/C++/Java cannot interpret strings as code at run-time.
That said, SystemVerilog does provide a C to simulator interface (VPI) that can provide access to identifiers via a string lookup if the tool knows at compilation time that you plan to use that. It has to create a database of identifier strings and preserve signal values that you plan to access so they are not optimized away.
But depending on what you need to do, you might be able to take advantage of tool specific debug and waveform dumping features to access signal names without having to write any C code.