In reply to dave_59:
However there’s just one problem: not enough users demand full compliance to any EDA language standard. IEEE 1364.1-2002 was never adopted by any vendor, and the standard was withdrawn.
Hm, that’s news to me. Quite disappointing actually, as the work was done, and it was voted on and accepted as an IEEE standard. I have a copy of the standard. My name’s on the working group. What’s the point in withdrawing the standard after it’s already been accepted? Anyway, I won’t pretend to understand how standards bodies work.
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There’s quite a bit more gray areas regarding synthesizable subset with SystemVerilog than within Verilog-2001. I could start a list myself. The language evolved quite a bit.
As I mentioned, I know this standardization task was brought up by one of the EDA trainers/instructors during the language development in the Accellera SV-EC/SV-BC working groups. I also know this caused quite a ruckus, even though there was substantial support (at least among the non-EDA tool vendor) members. As I read things, it looks like the task was harshly buried.
In the justification of not doing this work, you mention winding “up with 2 standards without uniform compliance”. As it is now we have N standards - each vendor defining their own (unpublished) subset. For every user to blindly fumble about to try and find.
What’s the point of standards bodies, if they don’t want to do the necessary work that helps all the end-users and industry as a whole?
Regards,
Mark