First of all, Thank you so much for advices.
But, I’ve checked my set() and get (). I could not find any fault yet… Everything seems all right. When I compile, Everything is ok even, But when I simulate. Same error again.
Here is my Test, And Config class as well:
// --------------------------Config class
import uvm_pkg::*;
import my_pkg::*; //import our package here
`include "uvm_macros.svh"
class my_config extends uvm_object;
`uvm_object_utils(my_config);
virtual Exc1_if config_vif; //virtual interface to driver
int iterations;
function new(string name = "");
super.new(name);
endfunction
endclass
// more information on Test class on ***** VerificationAcademy Basic UVM, session 6 video ******
// And Course Slide, Lecture 4
// ---------------------------------Test class (my_test1)
import uvm_pkg::*;
import my_pkg::*; //import our package here
`include "uvm_macros.svh"
class my_test1 extends uvm_test; // typically we start the sequences with a Test. *** VerificationAcademy Basic Session 6 Video
`uvm_component_utils(my_test1) // Register the test as a component
my_env my_env_h; // the test will instantiate the Environment
my_config m_config; // -----------------------------------------------
my_seq seq;
function new(string name, uvm_component parent=null);
super.new(name, parent);
endfunction: new
// -----------------------------------------------
function void set_config_params();
m_config = my_config::type_id::create("m_config");
if (!uvm_config_db #(virtual Exc1_if)::get(this, "","top_pif", m_config.config_vif))
`uvm_fatal("ALU test", "Can't read the VI - config_vif");
uvm_config_db #(my_config)::set(this, "", "my_config", m_config);
m_config.iterations = 10;
endfunction;
// -----------------------------------------------
function void build_phase(uvm_phase phase);
m_config = new();
super.build_phase(phase);
set_report_verbosity_level_hier(UVM_MEDIUM);
my_env_h = my_env::type_id::create("my_env_h", this);
set_config_params();
endfunction: build_phase
task run_phase (uvm_phase phase);
seq = my_seq ::type_id::create("seq"); // create an instance of our "sequence", in my case "my_seq"
phase.raise_objection(this);
seq.start ( my_env_h.sequencer_h); // Starting the test , the argument is the sequence that will start , *** VerificationAcademy Basic session 6 Video
phase.drop_objection(this);
endtask
endclass: my_test1