Extern function/task definition in generate-block scope within scope of class definition

SystemVerilog
,
4

In reply to nachumk:

Why is this not a workable solution?

module m # (parameter bit ME = 1) ();
class c();
  function void hello();
    if (ME) begin
      $display("Hello Me!");
    else 
      $display("Hello You!");
  endfunction
endclass

endmodule