In reply to stefaniecg:
First of all, there is no need to do this in Verilog/SystemVerilog - all vectors are implicitly extended or truncated to fit into the needed context.
But SystemVerilog has a cast operator that can be used to explicitly show your intent, or to change the context if it does not match what you want.
You can do
P'(expression). // changes the width of the expression to match the constant P
// - signedness remains the same
signed'(expression) // changes the signedness of an expression
unsigned'(expression) // - width remains the same
typename'(expression) // changes the width and signedness to match a user defined typename
// can also be used to reshape arrays and structs.