Execution of connect phase twice in simulation

In reply to mitesh.patel:

The strategy UVM has is seperating test from testbench. But the test can customize the testbench. Any modification will be executed prior to the run_phase. Then it is fix.
If you want to modify connections in your envrionemnt (testbench) you can define a new test doing this.
This approach is very structured and helpful for reuse.