Event vs. process

SystemVerilog
, ,
4

In reply to dave_59:

Hi Dave,

See example below from UVM test:



  process proc;

  fork begin
    proc = process::self();
    seq_inst[0] = stimulus_seq::type_id::create("seq_inst[0]");
    seq_inst[0].start(env_inst.agent_inst[0].sequencer, null);
  end
  begin
    seq_inst[1] = stimulus_seq::type_id::create("seq_inst[1]");
    seq_inst[1].start(env_inst.agent_inst[1].sequencer, null);
  end
  join_none
  
  wait (proc != null);
  proc.await();
  
  // Go forward in test execution after "proc" FINISHED

So, did this example open this question more?

-Vaino