In reply to bharath123:
I made certain modifications in my code as you suggested,It appears certain races.
///////////////////////////////////////////////////////////////////////////////////////
program main;
class event_c;
event ev1;
rand bit [4:0] my_var;
bit local_var;
task t_logic;
if(my_var < 20) begin
->ev1;
$display("variable in range my_var=%d",my_var);
end
else
$display("variable out of range my_var=%d",my_var);
my_new();
endtask:t_logic
task my_new;
forever@(ev1)
$display("my random variable is :%d",my_var);
endtask:my_new
endclass
initial begin
event_c evc;
for(int i=1;i<10;i++) begin
evc=new();
$display("Inside repeat");
evc.randomize();
evc.t_logic();
end
end
initial begin
#1000 $finish;
end
endprogram
/////////////////////////////////////////////////////////////////////
My simulation result as below:
$ irun event_dec.sv
irun(64): 15.10-s004: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
Recompiling… reason: file ‘./event_dec.sv’ is newer than expected.
expected: Thu Aug 11 12:04:59 2016
actual: Thu Aug 11 12:05:23 2016
file: event_dec.sv
evc.randomize();
|
ncvlog: *W,FUNTSK (event_dec.sv,28|18): function called as a task without void’().
program worklib.main:sv
errors: 0, warnings: 1
Caching library ‘worklib’ … Done
Elaborating the design hierarchy:
Top level design units:
main
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Building instance overlay tables: … Done
Generating native compiled code:
worklib.main:sv <0x38f1973e>
streams: 11, words: 10625
Building instance specific data structures.
Loading native compiled code: … Done
Design hierarchy summary:
Instances Unique
Programs: 1 1
Registers: 6 8
Named events: 0 1
Initial blocks: 2 2
SV Class declarations: 1 1
SV Class specializations: 1 1
Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv … Done
SVSEED default: 1
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> source /tools/apps/cadence/INCISIVE15.10.004-lnx86/tools/inca/files/ncsimrc
ncsim> run
Inside repeat
variable in range my_var=11
Simulation complete via $finish(1) at time 1 US + 1