In reply to Spriyada29:
There are couple of syntactical issues over here.
- You can not declare the variables anywhere in between the statements. Since the variables that are declared has a scope of a particular block, they must be declared at the top.
The variable declarations must be immediately after the function definition. Refer SystemVerilog IEEE 1800-2012, section 13. All variables in a task or function must be declared before any operation. A good practice is to always declare your variables at the top of function/block.
function out_data pre_processing(string temp_i);
bit temp_i_b[]; // Declare all the variables first
bit d[];
int k,d_zero;
bit tempor[];
bit [511:0]temp_out[];
int n;
int T=0;
int i=0;
int l;
// .. other variables declaration
pre_processing= new [temp_i.len()] ;
temp_i_b=new[24](temp_i_b);
temp_i_b[temp_i_b.size()-1:0]=temp_i.atobin();
As a side note, you can declare the variables at the start of begin…end block also. Refer to similar issue over here.
- I didn’t get the intention of these lines. They are syntactically incorrect. What is the use of “[]” over here?
tempor[]=temp_i_b << (k+d_zero);
foreach(d[i])
tempor[]={tempor,d[d.size()-i-1]};
- While creating the object, the arguments can be passed by name or by position. The object creation line is incorrect over here. Following are the methods to pass an argument to the function.
my_q=pre_processing(.temp_i("ABC")); // by name
my_q=pre_processing("ABC"); // alternative way, by position