Error loading the desing (Matlab - TB integration)

UVM
4

In reply to dirkh:

Hi Dirk and Srini,

First of all thanks for your answer :)

I have tried to modify the proposed vsim line but it did not work.

If I keep it like you mentioned Dirk it says I am trying to run a 64 bits file in a 32 bit machine. (I removed the -64 argument because I received an error. The line I tried to used, like in the qmw example, was:
"vsim -64 +UVM_TESTNAME=random_test_matlab -sv_lib qmw/qmw_sv/questa/qmw_client_64 top_optimized -do “qmw_demo.do” "
And the error I get is:

** Error: (vish-3296) Unknown option ‘-64’.

Use the -help option for complete vsim usage.

** Error: Error loading design

Error in macro ./run_matlab.do line 46

Error loading design

while executing

“error “Error loading design””

(procedure “vsim” line 140)

invoked from within

“vsim -64 +UVM_TESTNAME=random_test_matlab -sv_lib qmw/qmw_sv/questa/qmw_client_64 top_optimized -do “qmw_demo.do””

I thought of running the simulation as a 32 bit machine so I did:
vsim +UVM_TESTNAME=random_test_matlab -sv_lib qmw/qmw_sv/questa/qmw_client_32 top_optimized -do “qmw_demo.do”

With that I get the following error:

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ns Iteration: 23 Process: /uvm_pkg::uvm_phase::m_run_phases/#FORK#1847_f7d329a File: /home/antonio92/questasim/linux/…/verilog_src/uvm-1.1d/src/base/uvm_common_phases.svh

Fatal error in Function scrambler_pkg/base_test::end_of_elaboration_phase at tb_classes/base_test.svh line 27

I do not understand the last error as the base_test class is:


virtual class base_test extends uvm_test;
   env       env_h;
   uvm_sequencer #(sequence_item) sequencer_h;   

   extern function new (string name, uvm_component parent);
   extern function void build_phase(uvm_phase phase); 
   extern function void end_of_elaboration_phase(uvm_phase phase);
endclass

function base_test::new (string name, uvm_component parent);
   super.new(name,parent);
endfunction : new

function void base_test::build_phase(uvm_phase phase);
   virtual scrambler_bfm bfm;
   env_config env_config_h;
   
   if(!uvm_config_db #(virtual scrambler_bfm)::get(this, "","bfm", bfm))
     `uvm_fatal("TEST", "Failed to get the BFM");
   env_config_h = new(.bfm(bfm));
   
   uvm_config_db #(env_config)::set(this, "env_h*", "config", env_config_h);
   env_h = env::type_id::create("env_h",this);
endfunction : build_phase

function void base_test::end_of_elaboration_phase(uvm_phase phase);
   sequencer_h = env_h.scrambler_agent_h.sequencer_h; // I get the error right here...
endfunction : end_of_elaboration_phase

I guess the simulator cannot find exactly where the error is, because I do not understand where is the error there. In fact, I have been using the end_of_elaboration_phase like that before.

I also get the following warning, which I do not understand as my scrambler_dut it is compiled…

** Warning: (vopt-2008) Cannot find module or instance ‘scrambler’ specified in +cover option.

Thanks to both of you,
Antonio