Error: a variable index into the generate block 'reg_array' is illegal

SystemVerilog
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2

In reply to taihaichen:

The problem/solution is the same as in the other post you mention. The generate-for loop does not create true arrays that can be indexed with a dynamically changing variable. You must use constants or another generate-for loop to access reg_array. I would move the procedural-for loop into a generate for loop.

 for (genvar stage_index_=0; stage_index_<REG_COL_NUM; stage_index_++) begin
     always_ff @(posedge clk, negedge nreset)
                if (~nreset) 
                        reg_array[stage_index_].reg_col[0] <= 0;
                    
  end