Equivalent expression for b[=0]

SystemVerilog
,
8

In reply to Have_A_Doubt:

Will have to work on some alternative logic

I am currently trying the following


 bit simulatn_ends,clk ,a,  b;
 always #5 clk = !clk; 

  property ab4;
    @(posedge clk) a |=> ( !b throughout $rose( simulatn_ends )[->1] ) or strong( @(simulatn_ends) 1 ) ; 
  endproperty
 
  assert property(ab4) $display("T:%0t Pass",$time);
  
  initial begin
     #4;a=1;
    #10;a=0;
   #102;$finish(); 
  end
  
  final begin // Executes after $finish() is called in UVM Tb via uvm_top::run_test()
   simulatn_ends = 1;
  end

My understanding was on calling $finish(), only the final block and strong operator in effect will execute.Yet there is no pass once simulation ends