Equivalent expression for b[=0]

SystemVerilog
,
4

In reply to Have_A_Doubt:


 b[=1] is !b[*0:$] ##1 b[*1[ ##1 !b[*0:$]
//
 b[=0] is !b[*0:$] ##1 b[*0] ##1 !b[*0:$]
          !b[*0:$] ##1 !b[*0:$]  // reduced 
          !b[*0:$] 
// for the following
a |=> b[=0]
/* As !b[*0] is an empty sequence , it would never match right ?
  YES
So the assertion would pass at the earliest due to !b[*1] and the implicit first_match for the consequent 
Yes. */
//Typical use
a |=> b[=0] ##1 c
// I prefer to write it as 
a |=> !b[*0:$] ##1 c