In reply to tejasakulu:
Typically the monitors in your testbench sample the inputs/outputs of your design every clock cycle and send it out as a transaction to your checkers/scoreboards. The clock is implicitly imbedded in your transaction as you know that each transaction is sent on a clock edge. And if you have different clocks, you’ll have different types of transactions. The UVM encapsulates this in terms of agents/interfaces. This may seem overly complicated for just a simple timer, but starts making more sense in increasingly larger designs.