Equivalent construct in SV for modelling Reference model for Verification

In reply to tejasakulu:

Let me preface my answer by saying that I think you are taking the wrong approach in creating a reference model. It’s not supposed to be a duplicate of the RTL model and it does not need a clock. It needs to capture inputs as they arrive to the DUT and output as they exit the DUT. The fact that these occurrences come at clock edges should be irrelevant.

You can model any always block

always code;

becomes


fork 
  forever code;
join_none

and a continuous assignment

assign w = expr;

becomes

fork 
  forever @* w = expr;
join_none