Enum type generation with distributed wight

SystemVerilog
,
4

Hi Guy,

Dave’s solution is good but the percentage of no_error packets will be greater than 25%:

  • 25% because error_mode will be 0 in 25% of the cases
    • an additional percentage because no_error will also appear when error_mode is 1

The complete solution is:


  rand bit error_mode;
  rand Error_t Error_Type;

  constraint Error_Type_c {
    solve error_mode before Error_Type;

    error_mode dist {0:=25, 1:=75};

    error_mode == 0 -> Error_Type == no_error;
    error_mode == 1 -> Error_Type != no_error;
  }

Best regards,
Daniel.