Enum type generation with distributed wight

SystemVerilog
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2

In reply to guy.levi:

The best way to do this is to create a random error mode bit and put the distribution on that bit.

rand bit error mode;
rand Error_t Error_Type;
constraint Error_Type_c { error_mode dist {0:=25, 1:=75};
                          error_mode == 0 -> Error_Type == no_error;
                          solve error_mode before Error_Type;
                        }