In reply to uvmsd:
If at time 0 (or any other time afterward), clk_en && rest is false or unknown(x), your monitor gets into a 0-delay forever loop, which is a hang.
You should not mix different clock expressions, just use @(counter_vif.counter_cb);
You could change your clocking block signal directions to ‘inout’. Thet would allow you to both drive and sample them