In reply to chr_sue:
Hello chr_sue,
A follow up question on use of #0 in clocking block.
Let’s say that a TB component using the clocking block inside an interface is a reactive slave that drives a ready in response to valid from DUT, like an AXI bus. Ready could be driven 10 clock cycles after valid goes high, or it could be driven instantaneously so that the valid ready handshake completes in 1 clock cycle.
In case of instantaneous ready generation, behavior would be like a combinatorial equation where valid high result in ready high. Then the slave driver has to have the valid sampled in the observed region, right? Else the valid from DUT would have to wait for 1 more cock cycle.
What’s a good strategy in this case? Should the valid be taken out of interface clocking block all together, or should it be given #0 input skew in clocking block?
interface test_if(input clk);
logic valid;
logic ready;
clocking drv @(posedge clk)
default input #0;
input valid;
output ready;
endclocking
endinterface
class driver;
virtual test_if tb_if; //Virtual interface
//Run phase
@(tb_if.drv);
if(tb_if.drv.valid) tb_if.drv.ready <= 1;
endclass