Effect of clocking block on uvm driver/monitor

In reply to Mechanic:

With #0 you are stepping foreard in the SV event scheduler. Because you do not know where you are in this scheduleryou might disturb the correct processing of the assignments etc in the current time slot. I know this sounds a little bit theoretically but it is the truth.
Unfortunately I did not find a figure of the SV event scheduler I can put in here.
The clocking block is doing on the RTL level the same we are doing on the gatelevel when introducing a setup and hold time.
BTW the clocking block is an option and not a must. I have never used in my professional experoence and projects a clocking block.
Where does the sentence come from you are mentioning?