Hi Dave,
If possible could you please point me to your past recommended post?
I would like to understand what is the ideal way to tieoff the DUT signals during the run time.
Should I look for command line args in the tb_top and tie off the redundant DUT signals or is there any better approach to achieve this run time DUT configuration?
Thanks,
Somasekhar M
In reply to dave_59:
You can’t dynamically instantiate a module. If you instantiate all devices and selectively tie their inputs to GND you will not pay any run-time penalty, just some elaboration setup time.
What I have recommended in the past is to have a two-step flow where you use the randomization features to write a SystemVerilog package that is used in the second step to configure the DUT for running the test.
Dave