Dynamic cast Failure

UVM
3

In reply to rag123:

A bit is a two-state signal, while a logic is a four-state signal. If you attempt to cast a logic vector which contains an ‘x’ or ‘z’ to a two-state signal, you will get a casting error.

The below code will generate a $cast error:


import uvm_pkg::*;
`include "uvm_macros.svh"
 
 typedef enum bit[1:0] {IDLE, BUSY, NONSEQ, SEQ} transfer_t;
module top;
  transfer_t trans_type[];
  logic [1:0] HTRANS;
 
class transaction extends uvm_object;
   transfer_t tr_type[];
   `uvm_object_utils(transaction)
   function new (string name = "");
      super.new(name);
      tr_type = new[3];
   endfunction   
endclass
 
  transaction my_trans;
 
  initial begin
    my_trans = new("my_trans");
    trans_type = new[3];
    HTRANS = 'bx;
    $display("HTRANS = %0h", HTRANS);
    $cast (trans_type[0], HTRANS);
    $display("trans_type[0] = %0h", trans_type[0]);
    $cast (my_trans.tr_type[0], HTRANS);
    $display("my_trans.tr_type[0] = %0h", my_trans.tr_type[0]);
  end
endmodule