Hi,
I’m trying to create a test with reset.
When I’m trying to drive the signal via the virtual interface from the test sequence the value of the signal in the DUT is turning to XXX. (there is an initial block in the top where the reset signal is set to 1 after 20ns)
I tried to use force to the signal from the test sequence. the signal indeed changed to zero, but the simulation (it seems to be the clock) gets stuck.
What do I do wrong?
What is the correct way to drive reset signal?
Thanks!