In reply to chr_sue:
This is my top module:
module top;
import uvm_pkg::;
import pkg::;
//clk
bit clk;
always #10 clk=~clk;
// instantiating
serial_write in0(clk); // interface instance
cpu_write DUT(.clk(clk),.reset(in0.reset), .enable(in0.enable), .sin(in0.sin),.addr(in0.addr),.data(in0.data),.count(in0.count));
bind cpu_write: DUT serial_write b0(DUT.en); //bind
initial
begin
//set the virtual interface using the uvm_config_db
uvm_config_db #(virtual serial_write)::set(null,"*","vif",in0);// how to give bind instance
run_test();
end
endmodule