In reply to Coppola:
Would be great if you could put your example to EDAPlayground (edaplayground.com) to have an executable piece of code.
Only a few remarks:
(1) in your DUT you have your clock generator, but you generating only 1 edge.
(2) In the constructor of your config bals the constructor call to the base class is missimng. It should be
class dut_config extends uvm_object;
`uvm_object_utils(dut_config)
function new(string name = "dut_config");
super.new(name);
endfunction
virtual dut_if dut_vif;
endclass