In reply to dave_59:
In reply to jabreen:
A problem that I’ve seen with nested interface declarations is when you try to make a virtual interface out of it.
That may be the issue here (which I didn’t include in the snippets above). The error came from
a virtual interface reference when loading. Here is the full error from the original code:
# ** Fatal: (vsim-8451) ./wishbone/wb_bus_bfm_monitor.svh(56): Virtual interface resolution cannot find a matching instance for 'virtual wishbone_bus_bfm_if'.
# Global interface 'wishbone_bus_bfm_if' expected.
# Non-matching nested interface from 'wb_bus_wrapper' has instances:
# ./wishbone/wb_bus_wrapper.sv(157): wishbone_bus_bfm_if #() wb_bus_bfm_if()
(note that the original interface is also parameterized; that caused errors when I moved it, so I took it out (the parameter wasn’t used in the interface, so I’m not sure why it was there)).
So you’re saying that 23.8 allows tasks to be called with no compile-time indication of how the task is defined? That’s hard for me to get my head around, but I’m a relative newbie to Verilog and SV.
Also, I meant to give a link to the (original) code in my original post: https://verificationacademy.com/cookbook/download?file=/w/images/2/20/Uvm_Wb_mac_bfm_vif.tgz