In reply to bmorris:
I agree if you mean a database access means doing uvm_config_db::get() each time you create a class derived from uvm_sequence_item. What you can do is have the sequence that constructs the items get the configuration object once and pass a handle to that object to the item.
$ not currently allowed in a dist constraint. You have to realize that SystemVerilog was designed by a number of committees, and sometimes features created for one specific purpose do not always make it uniformly across the LRM.