Distribute with exclude some values systemverilog

SystemVerilog
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2

In reply to ashaboon:
You simply write additional constraints, which take precedence over the distribution.

constraint c{
  rand_val dist {signed'(-fact):= 1,
               [-fact+1 : fact-1]:/1 ,
                fact:=1};
  rand_val < cond;
  rand_val %2==0;
}