I have a question regarding Inter-Lane Skew Insertion in DPTX.
In the attached Figure 2-8 (Section 2.2.1), the spec states that data is “inter-lane skewed before it is handed over to the PHY Layer,” which makes it appear to be a Link Layer function.
However, in the attached Figure 3-23 (Section 3.5.1.5.1), Inter-Lane Skew Insertion is shown after the FEC encoder and is explicitly placed within the Main-Link PHY Layer Logical Sub-block, suggesting it is a PHY Layer function.
Therefore, I am confused about the intended architectural partitioning for a practical VIP implementation, should the inter-lane skew be applied:
- Before the Link/PHY boundary (In Link Layer), or
- Within the PHY data path (for example, after FEC encoding and before serialization)?