$display

SystemVerilog
,
12

In reply to SHRI12326:

Yes it is due to a race condition. Modify your code to:


module fork_join_none();

  int a,b,c;

  initial begin
    a=5;
    fork
      a=6;
    join_none
    $display("value of A before blocking stmt a=%d",a);
    b=0; //blocking statement
    #0;
    $display("value of A after blocking stmt a=%d",a);
  end
endmodule : fork_join_none

and you will get the desired effect.

As a sidenote, please don’t read the 3.1a SystemVerilog LRM except for historical purposes. The 2012 LRM has been made free for download: https://standards.ieee.org/getieee/1800/download/1800-2012.pdf