Combinationally sampling an input in clocking block - SystemVerilog - Verification Academy
In this post you mentioned the use of iff with clocking event.
@(cb iff ready) // Wait until ready
But the value sampled by iff is nondeterministic right?
Combinationally sampling an input in clocking block - SystemVerilog - Verification Academy
In this post you mentioned the use of iff with clocking event.
@(cb iff ready) // Wait until ready
But the value sampled by iff is nondeterministic right?