Disadvantage of sampling from clocking block

SystemVerilog
1

dut:

module dut (input clk, input in1, input in2, output reg out1, output out2);
    always @(posedge clk) begin
        out1 <= in1;
    end
    assign out2 = out1 & in2;
endmodule

dut_if:

interface dut_if();
    logic clk;
    logic in1;
    logic in2;
    logic out1;
    logic out2;
    clocking cb @(posedge clk);
        output in1;
        output in2;
        input out1;
        input out2;
    endclocking
endinterface

in this case, it is impossible to cover out1 == 1 & in2 == 1 if we design the driver which drives cb.in2 to 1 by only checking whether cb.out1 == 1 first right?

2

I do not understand the point of your question. What does the check whether cb.out1 == 1 have to do with clocking block? You would have the same problem with or without the clocking block if you mean you are waiting for cb.out1 == 1 before setting cb.in2 ==1.

3

Without clocking block I can sample the current value of cb.out1.

4

Combinationally sampling an input in clocking block - SystemVerilog - Verification Academy

In this post you mentioned the use of iff with clocking event.

@(cb iff ready) // Wait until ready

But the value sampled by iff is nondeterministic right?