Disable SVA on a Fail

SystemVerilog
,
2

You can use $assertoff or $assertkill in the else part of the assertion. The following code works for me.

DETECT_GLITCH : assert property (detect_glitch)
else
  $assertoff(0,DETECT_GLITCH);

// Output
"testbench.sv", 21: top.DETECT_GLITCH: started at 3ns failed at 3ns
	Offending 'top.my_func()'
Stopping new assertion attempts at time 3ns: level = 0 arg = DETECT_GLITCH (from inst top (testbench.sv:23))

Refer here for a similar question. Refer IEEE 1800-2012 Section 20.12 for system tasks of assertions.