Difference in output using 'within' V/S 'intersect' operator

SystemVerilog
,
9

In reply to ben@SystemVerilog.us:

Hi Ben,
I wanted to know what is the correct SVA terminology for the following

  1. When assertion passes, do we say that the consequent is a match OR consequent is true ?
  2. When assertion passes, do we sat that intersect/within operator was true OR intersect/within operator was a match ?