In reply to ben@SystemVerilog.us:
// An optimized simulator would recognized that there is no need to further evaluate
// the LHS since anything thread after (!a ##1 a ##1 !a ##1 a) is a no-match even if it
// length-match the RHS. This is because the LHS is a[=1].
// Thus, at the end of the thread of length 4 the simulator can declare a failure.
So as soon as 2nd $rose(gnt) is true, 5th and latter sequences don’t match .
Hence it’s interpreted as LHS sequence ends at time:125 resulting in assertion failure.