In reply to ben@SystemVerilog.us:
Ben ,
($rose(a), a_rose = realtime) |-> first_match( ##[0:] $rose(b) ) ##0 ( ($realtime - a_rose) > 2ns ); // OK
// Better coding
($rose(a), a_rose = realtime) |-> ##[0:] $rose(b)[->1] ##0 ( ($realtime - a_rose) > 2ns );
I am not clear why is clock delay ##[0:$] required for $rose(b) ?
Using it we don’t observe the failure at time:5 due to infinite ‘or’ sequence.
##[0:$] essentially will wait (till end of simulation) till sequence is true else it doesn’t throw an error.
Shouldn’t the following be sufficient ? :
($rose(a), a_rose = $realtime) |-> $rose(b)[->1] ##0 ( ($realtime - a_rose) > 2ns );