Difference in output using ##[0:$] $rose( b ) V/S $rose( b )[->1]

SystemVerilog
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In reply to Have_A_Doubt:


##[0:$] expr ##0 w //  is equivalent to 
##0   expr ##0 w or 
##1   expr ##0 w or 
##2   expr##0 w or 
..
##n   expr ##0 w 
/* if(expr==1) and w==0 then  you keep on looking for another possibility in later cycles. 
The consequent can never be a NO-MATCH because if no-match, then try for next cycle, maybe there will be  match. 
expr[->1] ##0 w // is equivalent to 
!expr[*0:$] ##0 expr  // Thus
// if (expr==1) in any cycle, then w must be true in the same cycle 
// Once expr==1 there cannot be cannot repeat cycle where expr==0
// the goto is like the 1st occurrence of the expression.

Ben Cohen
Ben@systemverilog.us
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