Difference between Virtual sequence and Virtual sequencers

In reply to syed taahir ahmed:

you have to use either virtual sequence or virtual sequencer(you may find examples online here verification academy too), to manage traffic on multiple interfaces in Soc, for example in your SoC you have USB, ETHERNET, AHB ports to drive traffic, then in your verification environment you will have all these three protocol UVCs and their sequences and sequencers will be controlled by virtual sequence or virtual sequencer that you are going to wrap above them.

First way with virtual sequence:
https://verificationacademy.com/cookbook/sequences/virtual

Second way:
The Virtual Sequencer - An Alternative Methodology For Running Virtual Sequences

An alternative methodology for running virtual sequences is to use a virtual sequencer(Sequences/VirtualSequencer | Verification Academy), which is a uvm_sequencer which contains the handles for the target sequencers. In this methodology, the virtual sequence is started on the virtual sequencer and it gets the handles for the target sequencers from the virtual sequencer. The limitation of this approach is that it is a fixed implementation which is very tightly coupled to the local hierarchy of an env and this adds complications with vertical reuse.

Hope this will be useful. Thank you.