In reply to dave_59:
In reply to UVM_LOVE:
When using `uvm_object_utils instead of field automation macros wrapped with uvm_object_utils_begin()~end(), it is up to you to provide the functionality that was automated for you, like the do_print() methods. Please see the link to the DVCon 2011 paper that suggests alternatives to the automation macros.
Thanks for reply Dave.
I’m currently modifying the uvm_field_* in TLM-10 A Single Port Analysis FIFO(1) - EDA Playground
I understood that I need to make a do_print() method as below,
//-------------------------------------------
// www.verificationguide.com
//-------------------------------------------
class transaction extends uvm_sequence_item;
//---------------------------------------
// Variable Declaration
//---------------------------------------
bit [7:0] dout;
rand bit [7:0] din;
rand bit [3:0] addr;
rand bit wr_rd;
rand bit [7:0] wdata;
//---------------------------------------
// Utility and Field macros
//---------------------------------------
/*
`uvm_object_utils_begin(transaction)
`uvm_field_int(dout,UVM_ALL_ON)
`uvm_field_int(din,UVM_ALL_ON)
`uvm_field_int(addr,UVM_ALL_ON)
`uvm_field_int(wr_rd,UVM_ALL_ON)
`uvm_field_int(wdata,UVM_ALL_ON)
`uvm_object_utils_end
*/
`uvm_object_utils(transaction)
virtual function void do_print(uvm_printer printer);
super.do_print(printer);
printer.print_field_int("dout", dout, $bits(dout), UVM_HEX);
printer.print_field_int("din", din, $bits(din), UVM_HEX);
printer.print_field_int("addr", addr, $bits(addr), UVM_HEX);
printer.print_field_int("wr_rd", wr_rd, $bits(wr_rd), UVM_HEX);
printer.print_field_int("wdata", wdata, $bits(wdata), UVM_HEX);
endfunction
//---------------------------------------
//Constructor
//---------------------------------------
function new(string name = "transaction");
super.new(name);
endfunction
endclass
But when I call do_print() method in object class, do_print() make an error as below,
trans.do_print(trans);
``` verilog
//-------------------------------------------
// www.verificationguide.com
//-------------------------------------------
class component_b extends uvm_component;
transaction trans;
uvm_tlm_analysis_fifo #(transaction) analy_fifo;
`uvm_component_utils(component_b)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
analy_fifo = new("analy_fifo", this);
endfunction : new
//---------------------------------------
// run_phase
//---------------------------------------
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
#100;
`uvm_info(get_type_name(),$sformatf(" Before calling analysis fifo get method"),UVM_LOW)
analy_fifo.get(trans);
`uvm_info(get_type_name(),$sformatf(" After calling analysis fifo get method"),UVM_LOW)
trans.do_print(trans);
phase.drop_objection(this);
endtask : run_phase
endclass : component_b
|
xmvlog: *E,TYCMPAT (component_b.sv,32|23): formal and actual do not have assignment compatible data types
If I do correctly call do_print() method , what am I supposed to fix ?
Where does "do_print()" method call? Could you guide me please?