I assume you mean the build_phase() method of classes derived from uvm_component. We recommend putting everything in the build_phase instead of new() because SystemVerilog does not allow you to completely override new(). Whenever you override a class, your overridden constructor has to call super.new() as the first statement (if you don’t, systemverilog will implicitly insert the call for you). By putting construction-like functionality into the build_phase(), when you override the class, you are not required to call super.build_phase(). This gives you a lot more flexibility as you override classes.
uvm_sequences has a body() method, not a build(). we recommend constructing sequence items in the body() method, not new() because you only need to construct an item once the sequence has started. But the UVM does not care when you do it.