Difference between -> and => in assertions

SystemVerilog
1

difference between : sig_a - > ##2 sig_b and sig_a = > ##2 sig_b in systemverilog assertions

2

→ immediately evaluated
=> next clock cycle evaluated
=> is equal to ->##1

u can say sig_a=>##2 sig_b as sig_a ->##3 sig_b

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3

To write a constraint that sig_a goes high, sig_b must follow within 3 clk cycles.

sig_a |-> [1:3] sig_b; // is this correct

4

Be careful with your syntax

  • A -> B is a logical implication operator equivalent to !A || B
  • A |-> B is an overlapping implication property operator. When A and B are both boolean expressions, it behaves the same as the logical operator, except that !A is considered a vacuous success.
  • A |=> B is non-overlapping implication property operator. It is equivalent to A|-> ##1 B. We recommend using the latter for consistency and clarity.
  • A -> ##[1:3] B means B must follow between 1 and 3 cycles.
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