Determining whether type parameter is Signed or Unsigned?

SystemVerilog
,
3

In reply to dave_59:

Hi Dave ,

**For a value parameter does the LRM define ::
(i) The sign
(ii) Whether its 2-state OR 4-state
**


module  top_tb ;

class  Main1 #( SIZE = 100 ) ;    //  [Q1]  Is  Value parameter  signed  OR  unsigned  ?? 
  
  function  void  display();
    $display(" In  Main1  $typename( SIZE )  is %0s " , $typename( SIZE ) ) ;
    $display(" In  Main1  SIZE   is %0d " , SIZE  ) ;   
  endfunction  
  
endclass  

typedef  int  unsigned  UINT32 ;

class  Main2 #( UINT32 SIZE = 128 ) ;  //  Value  parameter  is   Signed  OR  Unsigned ?
  
  Main1 #( SIZE ) m ;             //  [Q2]   Will  SIZE  be  Unsigned  ?? 
  
  function  new() ;
    m  =  new() ;  
  endfunction  
  
  function  void  display();
    $display(" In  Main2 $typename( SIZE )  is %0s " , $typename( SIZE ) ) ;
    m.display() ;
  endfunction  
  
endclass  

Main1 #( 2**32 - 1 )  m1  ;
Main2 #( 2**32 - 1 )  m2  ;

 initial   begin
   
   m1 = new() ;
   m2 = new() ;
   
   m1.display() ;
   m2.display();
   
 end  
  
endmodule

I Observe different Output across 3 Simulators

2 Simulators show :: **$typename( SIZE ) as 4-state type ( reg / logic )
whereas 3rd one show it as 2-state ( bit )
**

All 3 simulators show it as signed type with range [31:0]

**[Q2] Shouldn’t the specialization ‘m’ within class Main2 be unsigned as well ?
**