Design keyword: How to change the TOP module of a design

SystemVerilog
2

In reply to Curious_cat:

Section 33 of the LRM describes how to use configurations.

The example given is:


config cfg1; // specify rtl adder for top.a1, gate-level adder for top.a2
  design rtlLib.top;
  default liblist rtlLib;
  instance top.a2 liblist gateLib;
endconfig

The config name ‘cfg1’ is essentially an alias for rtlLib.top, except the top.a2 module uses the gateLib library version instead of the rtlLib version.

To simulate, you would specify ‘cfg1’ as the top level simulation block instead of ‘top’.