#delay is not working as expected in system verilog class (timescale issue)

SystemVerilog
,
3

In reply to dave_59:
test.sv

class test extends uvm_test;
 task t1();
  $printtimescale; 
  `uvm_info(get_name,$psprintf("Kranthi 1"),UVM_NONE);
   #2000ns;
  `uvm_info(get_name,$psprintf("Kranthi 2"),UVM_NONE);
 endtask
endclass

"TimeScale of $unit is 100 ps / 100 ps
Kranthi1 and kranthi 2 are printed with 200ns gap.

How do i make it work in class? I should keep test.sv in package ?