In reply to m0rph:
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@ben@SystemVerilog.us
Yes, you are absolutely right. I just wasn´t able to express myself properly.
As I am new to SystemVerilog I had to look up some few things to understand your code.
But now I mainly got it and its just great and very interesting. I have found favour in hardware programming and I want to learn more about systemverilog so I will surely have a look in your handbook.
Since you plan to migrate to hardware, and you are new to this, I do have a couple of very sincere recommendations because there is a lot more to hardware design than knowing a design language.
- Specifically, one needs to know and understand the various uses of things like the a)the types of counters, b) metastability, c) enhancing speed techniques, d)design of an error detection and correction, e) techniques in designing a CPU (microcode or FSM), synchronous and asynshronous FIFOs, etc:
- 2. Study my book Real Chip Design and Verification Using Verilog and VHDL, 2002In that book I address all these issues. It is available at Amazon (see VhdlCohen Publishing ).
However, at https://www.createspace.com/6334329 for a retail price of$80, with the discount code of 4XG6ECTE that drops the price to $54.40.
This book reflects a lot of my experiences and difficulties in applying an HDL to real designs and verification. Today, I would add assertions, and would stay ith SystemVerilog, but that is a different story.
3. A case in point about some of the tricky things in hardware design is demonstrated in my SVA book (in the formal verification chapter) on the design of complex traffic light controller. The link to those pages is as http://SystemVerilog.us/svabk4_Traffic_light.pdf
In my initial model, I used two loosely coupled FSM machines to control the EW and NS traffic. That got me into a lot of trouble as demonstrated by the assertions. I then switched to a two FSMs master/slave approach, and that worked well, as also verified with the assertions.
- Use assertions to clarify your requirements and to check your code. My book provides lots of examples. SystemVerilog Assertions Handbook, 4th Edition
https://www.createspace.com/5810350
USE 32% discount code: 4XG6ECTE
Subtotal $91.80
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115